9
FN4837.5
October 16, 2006
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6521) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180? The equations below relate the compensation
networks poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 6. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filters Double Pole (~75% F
LC
)
3. Place 2
ND
Zero at Filters Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifiers Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
Figure 7 shows an asymptotic plot of the DC/DC converters
gain vs. frequency. The actual Modulator Gain has a high
gain peak dependent on the quality factor (Q) of the output
filter, which is not shown in Figure 6. Using the above
guidelines should yield a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
P2
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the log-log graph of Figure 10 by
adding the Modulator Gain (in dB) to the Compensation Gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW)
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45?
Include worst case component variations when determining
phase margin.
ACPI Implementation
The three linear controllers included within the HIP6521 can
independently be shut down, in order to accommodate
Advanced Configuration and Power Interface (ACPI) power
management features.
To shut down any of the linears, one needs to pull and keep
high the respective FB pin above a typical threshold of
1.25V. One way to achieve this task is by using a logic gate
coupled through a small-signal diode. The diode should be
placed as close to the FB pin as possible to minimize stray
capacitance to this pin. Upon turn-off of the pull-up device,
the respective output undergoes a soft-start cycle, bringing
the output within regulation limits. On the regulators
implementing this feature, the parallel combination of the
feedback resistors has to be sufficiently high to allow ease of
driving from the external device. Considering the other
restriction applying to the upper range of this resistor
combination (see Output Voltage Selection paragraph), it is
recommended the values of the feedback resistors on an
ACPI-enabled linear regulator output meet the following
constraint:
To turn off the switching regulator, use an open-drain or
open-collector device capable of pulling the OCSET pin (with
the attached R
OCSET
pull-up) below 1.25V. To minimize the
possibility of OC trips at levels different than predicted, a
C
OCSET
capacitor with a value of an order of magnitude
larger than the output capacitance of the pull-down device,
has to be used in parallel with R
OCSET
(1nF recommended).
Upon turn-off of the pull-down device, the switching regulator
undergoes a soft-start cycle.
F
LC
1
2?/DIV>
L
O
C
O
?/DIV>
?/DIV>
--------------------------------------- -
=
F
ESR
1
2?nbsp ESR C
O
?/DIV>
?/DIV>
---------------------------------------- -
=
F
Z1
1
2?nbsp R
?nbsp 2 C1
?/DIV>
-----------------------------------
=
F
Z2
1
2?nbsp R
S1
R3
+
(
) C3
?/DIV>
?/DIV>
--------------------------------------------------------- -
=
F
P1
1
2?nbsp R
2
C1 C2
?/DIV>
C1 C2
+
--------------------- -
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
------------------------------------------------------ -
=
F
P2
1
2?nbsp R
?nbsp 3 C3
?/DIV>
-----------------------------------
=
FIGURE 7. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100K
10K
1K
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
F
LC
F
ESR
COMPENSATION
FREQUENCY (Hz)
GAIN
MODULATOR
GAIN
CLOSED LOOP
GAIN
20
V
IN
V
PP
------------
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
log
20
R2
R
S1
------------ -
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
log
2k&
R
S
R
P
?/DIV>
R
S
R
P
+
--------------------- -
5k&
<
<
HIP6521
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